A Model of Implementable SMT Processor on FPGA

Recent improvements of FPGA technology in its clock frequency, density and configuration cost enable to implement large-scale, complex circuit. In these days, many systems adopt FPGA so that the processor in FPGA will be required higher performance. This paper focuses on Simultaneous Multithreaded (SMT) architecture, one of multithreading technology that improves performance. We suggest implementable model of SMT processor on FPGA designing SMT processor and memory controller in hardware description language. As a result, a model that contains SMT processor, cache memory, memory controller is able to implement on single FPGA. Furthermore, we indicate efficient hardware use with internal Block RAM.